In this work, an alternative simulation approach for positive-tone photoresist modeling in grayscale lithography is developed, which is called the "three-state lithography model". The algorithm is adjacent to the state-of-the-art simulation programs, with a particular focus on a straightforward photomask desing procedure. The model performance is tested on spherical, pyramidal and chess field structures with a vertical resolution limit of 20-40 nm. Determining parameters and surface optimization of the produced 3D-topographies is presented in detail. Moreover, market analysis for grayscale lithography shows possibilities for the application of the semi-empirical approach developed in the present thesis. In addition, a modified process flow for the fabrication of a low-noise junction-gate field-effect transistor (JFET) is presented with lower process costs and reduced environmental footprint through the use of the grayscale lithography technique. The grayscale lithography model that is developed is suitable for the integration into commercial photomask design software or as add-on feature in state-of-the-art lithography simulators.    «

In this work, an alternative simulation approach for positive-tone photoresist modeling in grayscale lithography is developed, which is called the "three-state lithography model". The algorithm is adjacent to the state-of-the-art simulation programs, with a particular focus on a straightforward photomask desing procedure. The model performance is tested on spherical, pyramidal and chess field structures with a vertical resolution limit of 20-40 nm. Determining parameters and surface optimization...    »