Designing electronic (sub-)systems to be robust against ESD events is still not an easy task and a standard approach is not yet available. Accurate high frequency and high current models of all involved components are necessary to get precise system ESD simulation results, which help to optimize the ESD robustness of (sub-)systems. Often, the most critical devices in this context are ICs. There are typically no adequate IC ESD models available. A lot of requirements exist for such models: on the one hand, these IC models need to precisely replicate the IC behavior in case of ESD events. On the other hand, these models need to be quite compact to enable short computation times and protect the IP of the IC vendor. Additionally, a mechanism inside the model is desired to assess if the applied pulse can damage the IC. Available modeling methodologies mostly focus on special device types (e.g. bipolar transistors) and hence their usage is limited. The biggest disadvantage of existing IC modeling approaches is the need of measurements with complete ICs. These measurements are very resource intense in terms of equipment and staff. Typically, numerous pin-combinations need to be measured with various pulse lengths to get the necessary data for model generation. This work introduces a novel methodology to derive the IC ESD model out of the design data. A generic model architecture for different device types is the basis. This generic architecture allows to describe several devices with only one model. Complex circuits can be reduced to only one or a few model devices. Very compact ESD models of complete ICs are the result which demand only little computing resources and successfully protect the IP of the IC vendor. It is shown with the examples of two typical automotive ICs that the desired accuracy of ± 20 % is reached. The ESD clamping behavior and the transient behavior of the derived models match well with measurement results. Furthermore, the destruction limit of the single IC as well as the IC in small systems is accurately reproduced. Additionally, a comprehensive methodology to characterize and model the high current behavior of common mode inductors is presented. This methodology enables precise system ESD simulations in terms of transient response and destruction limit in case of ESD events for differential communication systems with common mode inductors.    «

Designing electronic (sub-)systems to be robust against ESD events is still not an easy task and a standard approach is not yet available. Accurate high frequency and high current models of all involved components are necessary to get precise system ESD simulation results, which help to optimize the ESD robustness of (sub-)systems. Often, the most critical devices in this context are ICs. There are typically no adequate IC ESD models available. A lot of requirements exist for such models: on the...    »